JPS6133225B2 - - Google Patents

Info

Publication number
JPS6133225B2
JPS6133225B2 JP55160654A JP16065480A JPS6133225B2 JP S6133225 B2 JPS6133225 B2 JP S6133225B2 JP 55160654 A JP55160654 A JP 55160654A JP 16065480 A JP16065480 A JP 16065480A JP S6133225 B2 JPS6133225 B2 JP S6133225B2
Authority
JP
Japan
Prior art keywords
subsystem
memory
applicant
subsystems
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55160654A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56124955A (en
Inventor
Misheru Jan Bienunyuu Jatsuku
Gaburieru Antowaanu Pieeru
Juuru Adonfu Bauu Robeeru
Rune Uino Danieru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SEE II II HANIIUERU BURU
Original Assignee
SEE II II HANIIUERU BURU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SEE II II HANIIUERU BURU filed Critical SEE II II HANIIUERU BURU
Publication of JPS56124955A publication Critical patent/JPS56124955A/ja
Publication of JPS6133225B2 publication Critical patent/JPS6133225B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Bus Control (AREA)
JP16065480A 1979-11-14 1980-11-14 Device for dividing central subsystem of data processing system into arbitrarily plural independent subsystes Granted JPS56124955A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7928076A FR2469752B1 (fr) 1979-11-14 1979-11-14 Dispositif de partage d'un sous-systeme central d'un systeme de traitement de l'information en plusieurs sous-systemes independants

Publications (2)

Publication Number Publication Date
JPS56124955A JPS56124955A (en) 1981-09-30
JPS6133225B2 true JPS6133225B2 (en]) 1986-08-01

Family

ID=9231670

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16065480A Granted JPS56124955A (en) 1979-11-14 1980-11-14 Device for dividing central subsystem of data processing system into arbitrarily plural independent subsystes

Country Status (5)

Country Link
US (1) US4472771A (en])
JP (1) JPS56124955A (en])
DE (1) DE3043012A1 (en])
FR (1) FR2469752B1 (en])
IT (1) IT1134273B (en])

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591975A (en) * 1983-07-18 1986-05-27 Data General Corporation Data processing system having dual processors
US4628463A (en) * 1984-03-05 1986-12-09 Georgia Tech. Research Institute Rapid-sweep electrochemical detector for chemical analysis of flow streams
US4870704A (en) * 1984-10-31 1989-09-26 Flexible Computer Corporation Multicomputer digital processing system
US4972338A (en) * 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
GB2189061A (en) * 1986-03-10 1987-10-14 Hitachi Ltd Management of system configuration data
US4807184A (en) * 1986-08-11 1989-02-21 Ltv Aerospace Modular multiple processor architecture using distributed cross-point switch
JPH02151926A (ja) * 1988-12-02 1990-06-11 Fujitsu Ltd 端末装置切替方式
US5317707A (en) * 1989-10-20 1994-05-31 Texas Instruments Incorporated Expanded memory interface for supporting expanded, conventional or extended memory for communication between an application processor and an external processor
US5708784A (en) * 1991-11-27 1998-01-13 Emc Corporation Dual bus computer architecture utilizing distributed arbitrators and method of using same
US5471609A (en) * 1992-09-22 1995-11-28 International Business Machines Corporation Method for identifying a system holding a `Reserve`
FR2724243B1 (fr) 1994-09-06 1997-08-14 Sgs Thomson Microelectronics Systeme de traitement multitaches
US5848231A (en) * 1996-02-12 1998-12-08 Teitelbaum; Neil System configuration contingent upon secure input
DE112005001869A5 (de) * 2004-08-11 2007-07-12 Netchilli Gmbh Vorrichtung und Verfahren zum Konfigurieren einer Datenverarbeitungsanlage

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1250659B (de) * 1964-04-06 1967-09-21 International Business Machines Corporation, Armonk, NY (V St A) Mikroprogrammgesteuerte Datenverarbeitungsanlage
US3480914A (en) * 1967-01-03 1969-11-25 Ibm Control mechanism for a multi-processor computing system
US3544973A (en) * 1968-03-13 1970-12-01 Westinghouse Electric Corp Variable structure computer
US3573852A (en) * 1968-08-30 1971-04-06 Texas Instruments Inc Variable time slot assignment of virtual processors
US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
US3812468A (en) * 1972-05-12 1974-05-21 Burroughs Corp Multiprocessing system having means for dynamic redesignation of unit functions
JPS5420299B2 (en]) * 1974-06-03 1979-07-21
FR2286439A1 (fr) * 1974-09-25 1976-04-23 Data General Corp Appareil de traitement de donnees a recouvrement et imbrication des operations de transfert de donnees
US4014005A (en) * 1976-01-05 1977-03-22 International Business Machines Corporation Configuration and control unit for a heterogeneous multi-system
US4171536A (en) * 1976-05-03 1979-10-16 International Business Machines Corporation Microprocessor system
US4070704A (en) * 1976-05-17 1978-01-24 Honeywell Information Systems Inc. Automatic reconfiguration apparatus for input/output processor
US4096571A (en) * 1976-09-08 1978-06-20 Codex Corporation System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority ranking

Also Published As

Publication number Publication date
FR2469752A1 (fr) 1981-05-22
DE3043012C2 (en]) 1988-06-23
JPS56124955A (en) 1981-09-30
IT8025981A0 (it) 1980-11-14
US4472771A (en) 1984-09-18
FR2469752B1 (fr) 1986-05-16
IT1134273B (it) 1986-08-13
DE3043012A1 (de) 1981-06-25

Similar Documents

Publication Publication Date Title
US4091455A (en) Input/output maintenance access apparatus
US4084234A (en) Cache write capacity
US4443846A (en) Dual port exchange memory between multiple microprocessors
US6233635B1 (en) Diagnostic/control system using a multi-level I2C bus
US3702462A (en) Computer input-output system
US4124891A (en) Memory access system
EP0855057B1 (en) Address transformation in a cluster computer system
EP0121373A2 (en) Multilevel controller for a cache memory interface in a multiprocessing system
EP0155443B1 (en) Microocomputer data processing systems permitting bus control by peripheral processing devices
US5857080A (en) Apparatus and method for address translation in bus bridge devices
US5136500A (en) Multiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memories
GB2166271A (en) Method of appointing an executive in a distributed processing system
JPS6133225B2 (en])
US4896256A (en) Linking interface system using plural controllable bidirectional bus ports for intercommunication amoung split-bus intracommunication subsystems
EP0194415A2 (en) Bus to bus converter
GB2211326A (en) Address bus control apparatus
JPS62182862A (ja) 大容量メモリおよび該大容量メモリを具備するマルチプロセツサシステム
US3560937A (en) Apparatus for independently assigning time slot intervals and read-write circuits in a multiprocessor system
GB2085624A (en) A coupling equipment for the control of access of data processors to a data line
JPH01298457A (ja) コンピュータシステム
US4604709A (en) Channel communicator
EP0067519B1 (en) Telecommunications system
JPH0227696B2 (ja) Johoshorisochi
JPH03238539A (ja) メモリアクセス制御装置
EP0391537A2 (en) Lock converting bus-to-bus interface system